1. Introduction

Moore’s Law

Variation of Processors

Signals

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Busses

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2. Numeric Representation (1)

Bases of Numbers \text{value} = \sum_{i=0}^{N-1}{\text{symbol}_i\times\text{base}^i}

Word Size

Base Conversion - from decimal to base b

Arithmetic

Negative Numbers - Signed Magnitude

Negative Numbers - Two’s Complement

Negative Numbers - Biased Form

3. Numeric Representation (2)

Binary Multiplication

Multiplication In Binary

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Unsigned Binary Multiplication Algorithm

Initialise partial product of 2n-bits to 0
Repeat n times:
	If LSB of multiplier = 1:
		Add multiplicand to n most significant bits of partial product
	partial product >>= 1
	multiplier >>= 1
int_2n pp = 0;
for (int i = 0; i < n; i++) {
	if (pp & 1 == 1)
		pp += multiplicand << n;
	pp >>= 1;
	multiplier >>= 1;
}

Multiplication in Signed Binary - Signed Magnitude

Multiplication in Signed Binary - Two’s Complement

Initialise partial product of 2n-bits to 0
multiplier <<= 1
Repeat n times:
	If last two bits of multiplier == 10:
		Subtract multiplicand from partial product's n most significant bits
	If last two bits of multiplier == 01:
		Add multiplicand from partial product's n most significant bits
	partial product >>= 1
	multiplier >>= 1
int_2n pp = 0;
for (int i = 0; i < n; i++) {
	if (multiplier & 0b11 == 0b10)
		pp -= multiplicand << n;
	if (multiplier & 0b11 == 0b01)
		pp += multiplicand << n;
	pp >>= 1;
	multiplier >>= 1;
}

Fractional Numbers

Fixed Point

Floating Point - IEEE Standard 754-2008 Float (binary32)

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Arithmetic with Fractional Numbers

We write A = a * 2**e1, B = b * 2**e2

if (abs(e1 - e2) > p + 1)
	return; we are done.

// shift mantissa to make exponents match
while (e1 < e2):
	a >>= 1;
	e1++;
while (e2 > e1):
	b >>= 1;
	e2++;

// we now have the exponents equal
m = a + b;
if (over range):
	m >>= 1;
	e1++;
	if (e1 > max): Exponent Overflow Error
else if (under range):
	m <<= 1;
	e1--;
	if (e1 < min): Exponent Underflow Error
else:
	return; we are done.

IEEE 754 Multiplication

4. Introduction to Digital Logic

Logic Gates

Negation Operator

AND Operator

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OR Operator

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XOR Operator

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Logic Gate Chips

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Translating Boolean Logic

Boolean Equation

Laws of Boolean Algebra

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Karnaugh Maps

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5. Computational Logic (1)

Universal Gates

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1-Bit Half Adder

int sum = a ^ b;
int carry = a & b;

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1-Bit Full Adder

int inter = a ^ b;
int sum = inter ^ carry_in;
int carry_out = (a & b) | (carry_in & inter);

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N-Bit Full Adder/Subtractor

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6. Computational Logic (2)

Decoders and Encoders

Decoders

Screenshot

Encoders

NOTE: There are two types of decoders and encoders: Active low and active high.

Active Low - Selected output is a 0, other values are 1 Active High - Selected output is a 1, other values are 0

Screenshot

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Multiplexers and De-Multiplexers

Multiplexer (MUX)

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De-Multiplexer (DE-MUX)

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3-State Logic

Three-State Logic

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Busses

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NOTE: We can also use 3-state logic to redesign the multiplexer, by connecting the output of the normal MUX circuit to three-state-logic to enable signals to go onto the output line

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Integrated Circuits

Propagation and Delay

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Logic Integrated Circuits

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7. Sequential Logic

Introduction

Computational vs Sequential Logic

Terminology

Latches and Flip Flops

SR (Set-Reset) Latch

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SR Latch with Enable

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D (Delay) Latch

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D Latch with Enable

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D Flip Flop

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More Types of Flip Flops

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Registers and Counters

N-Bit Register

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N-Bit Shift Register

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N-Bit Counter

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8. Introduction to Memory Systems

Memory Hierarchy

Choosing Memory Types

Memory Hierarchy

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Registers

Cache

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Main Memory

Static RAM:

Dynamic RAM:

Advantages of SRAM:

Advantages of DRAM:

Screenshot

Chip Organisation

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9. Long Term Memory

Hard Drives (HDDs)

Overview

Magnetism Strategies

Tracks and Sectors

Screenshot Screenshot

Performance t_{\text{access}} = t_{\text{seek}} + t_{\text{latency}} + t_{\text{settle}} + t_{\text{read}}

Optical Disks

Overview

Screenshot

Data Encoding

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Performance

Writing Data

Better Optical Disks

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10. Errors in Memory

Introduction

Errors & Noise

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Single Errors

Overview

Parity

Burst Errors

Overview

Checksum

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Block Level ECC

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In-Word Correction Codes

Hamming Codes

Overview

Computing

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Checking

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Hadamard Codes

Overview & Process

Computing the Matrix

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Efficiency

11. Introduction to Assembly

Fundamentals of a Processor

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Register Transfer Language

Overview

Instruction Fetching

  1. [MAR] <- [PC]
  2. [PC] <- [PC] + 1
  3. [MBR] <- [MS([MAR])]
  4. [IR] <- [MBR]
  5. [CU] <- [IR(opcode)]

Fetch and Execute (adds a constant byte to D0)

  1. [MAR] <- [PC]
  2. [PC] <- [PC] + 1
  3. [MBR] <- [MS([MAR])]
  4. [IR] <- [MBR]
  5. [CU] <- [IR(opcode)]
  6. [MAR] <- [PC]
  7. [PC] <- [PC] + 1
  8. [MBR] <- [MS([MAR])]
  9. [ALU] <- [MBR] + [D0]
  10. [D0] <- [ALU]

RISC-V Architecture

Overview

Instruction Set Format

Screenshot Screenshot

Assembly Syntax

RISC-V Instruction Set

Instruction Set

Arithmetic

Logic

Shifts

Branches

Jumps

Sets

Memory

System Control

12. Introduction to C

Comparison to Other Languages

Comparison to Assembly

Comparison to Java

Basics

Data Types

NOTES:

Pointers

Memory Management

Arrays

Strings

13. Introduction to I/O

Memory Mapped I/O

Memory Mapped I/O

Screenshot Screenshot

Advantages

Disadvantages

Direct Memory Access (DMA)

Overview

Operation Overview

  1. I/O sends request to DMAC
  2. DMAC sends request to CPU
  3. CPU initialises DMAC
  4. DMAC requests use of busses
  5. CPU sends DMA Acknowledge when read to surrender busses
  6. DMAC sends Acknowledge to transfer data

Screenshot

DMA Organisation

Operation Modes

14. Synchronous I/O

Motivations

Polling

Types of Polling

Screenshot

Advantages

Disadvantages

Handshaking

Motivation

Screenshot

Timing Diagram

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6522 VIA

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Interrupts

Motivation

Sequence

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Nesting

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Examples

Advantages

Disadvantages

Conclusion

15. Case Study: Ethernet

Overview

Overview

Life of 802.3

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Base Notation

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CSMA/CD

CSMA/CD

Algorithm

  1. If medium is idle, transmit. Otherwise go to 2
  2. If the medium is busy, continue to listen until the channel is idle, then transmit immediately
  3. If a collision is detected during transmission:
  4. If there have been too many attempts, stop attempting transmission
  5. Backoff for a period of time, then go to 1

Screenshot

Wires, Categories

Types of Cables

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Categories

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Twisted Pairs

Overview

EMI Emission

EMI Absorption

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Shielding, Connectors

Unshielded and Shielded Pairs

Screenshot Screenshot

Connectors

ScreenshotScreenshot

Straight Through and Crossover

Motivation

Straight Through, Crossover

Screenshot

Auto MDI-X

Motivation

Screenshot

Algorithm

  1. Both stations pick a number between 1 and 2048 (2^{11}
  2. If the number picked is even, use MDI
  3. If the number picked is odd, use MDIX
  4. Transmit some data down the lines
  5. If transmission is successful, then stop
  6. If transmission is unsuccesful, then:
    1. Wait 62 \pm 2 ms
    2. Pick a new number using Linear Feedback Shift Register (LFSR) as outline in 802.3 40.4.4.2
    3. Go to 2

Linear Feedback Shift Register

16. Processor Architecture

Microprocessor Organisation

Common Components

Control Unit

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Arithmetic and Logic Unit

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Turing Completeness

Micro and Macro Instructions

Micro Instructions

**Signal Timing Assumptions

Control Signals

Hardware Control Unit

Overview

Sequencer

Screenshot

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Advantages

Disadvantages

Microprogrammed

Overview

Terminology

Screenshot

Advantages

Disadvantages

17. RISC & CISC Processors

RISC

Motivation

Description

Example - ARM processors

ScreenshotScreenshot

Advantages

Disadvantages

CISC

Motivation

x86 Architecture

Intel 8080

Advantages

Disadvantages

Multithreading and Multicore Systems

Threading

Multithreaded Systems

Problems with Multithreading

Cores

Multicore Systems

Multithreaded & Multicore

18. Case Study: 68K

68K Architecture

Overview

Memory Registers

Screenshot

Internal Architecture

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68K Assembly

68K Assembly

Subroutines

Addressing Modes

  1. Data or Address Register Direct
  2. Immediate Addressing
  3. Absolute Addressing
  4. Indirect Addressing
  5. Relative Addressing

FDE Final Form

Screenshot

19. Achieving Performance

Measuring Performance

Time T_{\text{execute}} = N_{\text{inst}} + \frac{1}{W_{\text{inst}}} \times \text{CPI} \times T_{\text{cyc}}

FLOPs

Memory Bandwidth

\text{MB} = \frac{\text{Memory}}{T}

Benchmarks

Pipelining

Overview

Five Sections of Instructions

Screenshot

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Hazards

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Data Dependency

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Branches

Cache Organisation

Motivation

Direct-Mapped Cache

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Associative-Mapped Cache

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Set Associative Mapped Cache

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20. Considerations of Processor Design

Engineering Limitations

Manufacturing

Interconnects

Transistors

Energy Limitations

Utilisation Wall

Clock Speeds

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Cooling

Parallelisation Limitations

Amdahl’s Law

S_\text{latency}(s) = \frac{1}{(1-p) + \frac{p}{s}}

3D

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Other Considerations

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Quantum

Quantum

21. The Future of Processors

High Bandwidth Memory

Overview

MCDRAM

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HBM2

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ARM Marvell ThunderX2

Specialist Cores

Overview

ARM’s big.LITTLE architecture

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Apple M Series chips

Other

GPUs

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FPGAs

Heterogenous Computing

Overview

OpenMP 4.0/4.5/5.0

SYCL